Phase Locked Loop Node

The Phase Locked Loop Node sounds like a textbook that escaped from an electronics lab, but the idea is friendly: it takes one sigma schedule and nudges it toward matching another. You give it an input_sigmas sequence and a reference_sigmas sequence, and it slowly corrects the input so its "phase" - the timing and shape of its ups and downs - lines up with the reference. The README's framing is synchronization, and that's roughly what a real PLL does in a circuit; this is the sigma-schedule version.

When would you use that? Practically: you've drawn a custom waveform schedule you like, but its timing doesn't quite align with a reference schedule you're comparing against - or you have two generator outputs and want one to track the other instead of fighting it. It's the most specialized node in the SigmaWaveFormNodes pack, and it's honestly the least likely one you'll reach for. Know what it's for, file it away, move on.

How it actually works

The code keeps the loop simple. For each step, it accumulates a running error between reference and input:

phase_error += reference[i] - input[i]
correction = lock_factor * phase_error
locked[i] = input[i] + correction

So the correction is integrated, not applied sample-by-sample - small persistent differences between the two schedules accumulate into a growing nudge. That's the PLL behavior: it locks on over time rather than snapping instantly. After the loop, the whole output is clipped to ±frequency_range.

The two knobs:

• lock_factor (0–1, default 0.5) - how hard the loop pushes toward the reference. Low values mean a slow, gentle lock; 1.0 means it hammers the correction in.
• frequency_range (0.1–10, default 1.0) - the output clip limit.

Output is locked_sigmas, and both inputs plus the output are plain SIGMAS.

Installing it

Bundled with the pack - ComfyUI Manager search "SigmaWaveFormNodes", or:

cd ComfyUI/custom_nodes
git clone https://github.com/BenNarum/SigmaWaveFormNode

Restart ComfyUI. numpy + torch only; no models, no downloads.

The two traps

Lengths must match. The loop walks over the input's length and indexes the reference with the same index, so a reference shorter than the input throws an IndexError the moment it runs out, and a longer one silently ignores the tail. Always route both sequences through something that guarantees equal length - same steps value on the same generators is the easy path.

The output is hard-clipped to ±frequency_range. The default of 1.0 is small. If your sigmas are running at magnitude 3 (the default amplitude of the pack's own generators), the clip will flatten the entire signal into a box shape and the PLL becomes a square-wave maker. Crank frequency_range well above your sigma magnitudes - try 10 - or you'll spend a confusing hour wondering why your "locked" schedule is a rectangle.