CMK Combined ControlNet Bypass Gate
One gate, two architectures, and a hybrid special case
- PROCESS SDXL BYPASS
- PROCESS ZIT BYPASS
- IMAGE BYPASS
- LOG BYPASS
- PROCESS SDXL ACTIVE
- PROCESS ZIT ACTIVE
- IMAGE ACTIVE
- LOG ACTIVE
- DIAGNOSTIC ACTIVE
- PROCESS SDXL
- PROCESS ZIT
- IMAGE
- LOG
- diagnostic
CMK Flow keeps three generation paths technically separate: SDXL, Z-Image Turbo, and HYBRID (compose on SDXL, finish on Z-Image Turbo). That's a good design until you want one ControlNet checkbox to serve all of them. This node is where that gets sorted out.
What it does
The Combined gate is the two-architecture version of the pack's ControlNet bypass gate. Where the plain gate picks between one SDXL ControlNet result and its untouched input, this one picks between two results - an SDXL process and a Z-Image-Turbo process - plus the image and log that go with them, and it does it lazily so the losing branch never runs.
It's CMK/Developer/Boundary & Cache with DEV_ONLY set, so you'll meet it inside the shipped CMK workflows rather than in a tutorial. You have one boolean, ENABLE, and two parallel sets of inputs: a BYPASS set and an ACTIVE set, each carrying PROCESS SDXL, PROCESS ZIT, IMAGE, LOG. Outputs mirror that: PROCESS SDXL, PROCESS ZIT, IMAGE, LOG, diagnostic.
The mechanism, including the weird bit
Every optional input is lazy, so check_lazy_status decides what gets evaluated.
ENABLEoff → it asks only for the bypass legs (PROCESS SDXL BYPASS,PROCESS ZIT BYPASS,LOG BYPASS). Nothing upstream of the ControlNet module is evaluated; both processes come through untouched.ENABLEon → it resolves the SDXL side first, on purpose. The SDXL process carries a hybrid marker, and the gate reads that marker before it decides what to do with the ZIT leg.
That's the interesting case. In HYBRID mode, ControlNet belongs exclusively to the SDXL composition phase - the gate then requests PROCESS ZIT BYPASS rather than PROCESS ZIT ACTIVE, so the Z-Image Turbo finisher keeps its untouched contract while SDXL gets the structure guidance. The result gets labelled HYBRID SDXL ACTIVE / ZIT BYPASS in the logs so you can see which branch of the logic fired. Anywhere else, it's a straight active/active pair.
When ENABLE is off, diagnostic is filled with an ExecutionBlocker: no fabricated diagnostics from branches that never executed. When it's on, the diagnostic comes from the active SDXL leg and a missing one is treated as an error rather than swallowed.
Install
Manager: search CMK Flow → install the CMKFlow entry → restart. Manual, from the folder holding main.py:
git clone https://github.com/CMKFlow/cmk_nodes.git custom_nodes/cmk_nodes
python3 custom_nodes/cmk_nodes/scripts/install_cmk_requirements.py
You're looking for CMK dependency check: OK. The pack needs ComfyUI's Vue Nodes / Nodes 2.0 mode enabled for its dynamic nodes to render properly. CMK Flow is a single-author GPL-3.0 project (Carsten Kirschner, open-sourced July 2026) with a very small user base - the upside is that it's genuinely its own implementation rather than a wrapper; the downside is that when the gate complains, the source is your documentation.
Issues worth knowing
The gate raises rather than degrading gracefully: if the selected side is missing a PROCESS, IMAGE or LOG, you get a ValueError naming the label it wanted ("missing the BYPASS result" / "missing the ACTIVE result" / "missing the HYBRID SDXL ACTIVE / ZIT BYPASS result"). That's usually an unwired socket, not a bug. Both the SDXL and the ZIT bypass legs need to be connected even when you never intend to use ControlNet, because the disabled path reads them.
If you're chasing a mysterious quality difference between a HYBRID run and a pure SDXL run, check the log line first: the hybrid branch silently discards the ZIT ControlNet leg by design, so a ZIT-only ControlNet setting will do nothing in that mode. That's not a bug, and it's the kind of thing you can lose an hour to.
Inputs (10)
| Name | Type | Default | Description |
|---|---|---|---|
| ENABLE | BOOLEAN | false | — |
| PROCESS SDXL BYPASSopt | CMK_PROCESS_SDXL | — | |
| PROCESS ZIT BYPASSopt | CMK_PROCESS_Z_IMAGE | — | |
| IMAGE BYPASSopt | IMAGE | — | |
| LOG BYPASSopt | CMK_LOG_PIPE | — | |
| PROCESS SDXL ACTIVEopt | CMK_PROCESS_SDXL | — | |
| PROCESS ZIT ACTIVEopt | CMK_PROCESS_Z_IMAGE | — | |
| IMAGE ACTIVEopt | IMAGE | — | |
| LOG ACTIVEopt | CMK_LOG_PIPE | — | |
| DIAGNOSTIC ACTIVEopt | CMK_DIAGNOSTIC | — |
Outputs (5)
| Name | Type | Description |
|---|---|---|
| PROCESS SDXL | CMK_PROCESS_SDXL | — |
| PROCESS ZIT | CMK_PROCESS_Z_IMAGE | — |
| IMAGE | IMAGE | — |
| LOG | CMK_LOG_PIPE | — |
| diagnostic | CMK_DIAGNOSTIC | — |