ComfyUI-XPU-CacheClean

ComfyUI-XPU-CacheClean

🧹 VRAM cache clean node for Intel Arc (XPU), with CUDA fallback.

Design inspired by the cache_clean option in ComfyUI-Qwen3TTS-XPU: clear the XPU allocator cache before/after each generation to prevent leftover buffers from accumulating and triggering UR_RESULT_ERROR_OUT_OF_RESOURCES (level_zero error 40) OOM.

中文版 README (Chinese)

Why this node

The cache-clean branch of ram-vram-purge-windows's VRAM_Purge node depends on torch.cuda.is_available() — which is always False on XPU, so the cache cleanup never ran; only unload_all_models() (hard unload) executed. This node fixes that:

• soft: torch.xpu.empty_cache(), keeps models loaded → warm start, ≈0 cost
• hard: unload_all_models() + soft clean + gc — the XPU-compatible VRAM_Purge

Install

cd ComfyUI/custom_nodes
git clone https://github.com/hqh330/ComfyUI-XPU-CacheClean.git

Restart ComfyUI, search XPU Cache Clean.

Usage

| Parameter | Description | |------|------| | trigger | Connect any link to trigger cleaning; data passes through unchanged | | mode = soft | Cache only, warm start; place before heavy nodes (VAE decode / audio model load) | | mode = hard | Unload all models; place at stage transitions |

Recommended in big-model (H3-class) workflows:

1. soft before each VRAM-heavy stage (reduces allocator fragmentation)
2. hard at stage transitions (replaces the original VRAM_Purge)

Outputs report (STRING): VRAM stats before/after cleaning, connect to a text display.

Two-stage workflow ordering (key usage)

trigger_out is a * (universal) type output — connectable to any input of any node. Use it to guarantee execution order for in-workflow two-stage designs:

Stage A: TE encode → ConditioningIO(save) → LatentIO(save)
                    ↓ link (filename)
          XPU_CacheClean(hard)  ← unload all models + clear VRAM (TE/VAE freed)
                    ↓ link (trigger_out → any input of a Stage B load node)
Stage B: ConditioningIO(load) → LatentIO(load) → sample → decode

Key points:

• Order comes from links, not groups: groups are visual only; use trigger_out links to ensure Stage B runs after the unload
• Placement: hard goes after Stage A's save and before Stage B's load

Compatibility

• XPU first (torch.xpu), CUDA fallback
• Uses official comfy.model_management.soft_empty_cache() (XPU-compatible)
• No intel_extension_for_pytorch required

Publishing (Registry)

Meets the official ComfyUI custom node spec (pyproject.toml + LICENSE + README). Steps:

1. Push to a GitHub repository
2. pyproject.toml Repository is pre-filled with https://github.com/hqh330/ComfyUI-XPU-CacheClean
3. Submit at registry.comfy.org

License

MIT